The Active matrix method is one of various display methods for a liquid crystal display apparatus. The active matrix method, which attains a very fine display, uses TFTs (Thin Film Transistor) as switching elements.
In a liquid crystal display apparatus using the active matrix method, TFTs are tuned ON, line by line, in accordance with a scanning signal outputted from a gate driver. Via the TFT, a driving voltage is applied from a source driver to a pixel electrode connected to a drain of the TFT thus turned ON. Whereby, an electric charge is accumulated in a pixel capacitor between the pixel electrode and a counter electrode. This changes light transmittance of a liquid crystal, whereby display is performed.
One of applicable methods for performing gradient display in such liquid crystal display apparatus is a method in which a driving voltage outputted from a source driver is supplied as a gradient display voltage, which is in accordance with brightness of a pixel of a display object.
Here, an arrangement of the source driver is described referring to FIG. 13. A source driver 1010 shown in FIG. 13 receives, as inputs, a start pulse signal SP, a clock signal CK, digital display data DR, DB, a latch signal LS, and a reference voltage VR.
Each digital display data DR, DG, DB (for example, respectively having 6 bits), which are transmitted from a controller (control circuit), are latched by an input latch circuit 1011, temporally. Note that the digital display data DR, DG, and DB respectively correspond to red, green, and blue.
On the other hand, the start pulse signal SP for controlling transmission of the digital display data is, in synchronism with the clock signal CK, transmitted through a shift register circuit 1012 and outputted as a start pulse signal SP (a cascade output signal S) from a last stage of the shift register circuit and to a source driver, which is a next stage of the last stage of the shift register circuit.
In synchronism with output signals from respective stages of the shift register circuit 1012, the digital display data DR, DG, and DB, which have been latched by the input latch circuit 1011, are temporally stored in a sampling memory circuit 1013 in a time-sharing manner, and outputted to a hold memory circuit 1014, which is a next stage of the sampling memory circuit 1013.
When the digital display data that corresponds to a pixel in a horizontal line of a screen is stored in the sampling memory circuit 1013, the hold memory circuit 1014 receives an outputs signal from the sampling memory circuit 1013 in accordance with a horizontal synchronizing signal (latch signal LS), and outputs, to a level shifter circuit 1015, which is a next stage of the hold memory circuit 1014, the output signal from the sampling memory circuit 1013. Further, the hold memory circuit 1014 keeps the display data until a next horizontal synchronizing signal is inputted.
The level shifter circuit 1015 is a circuit for converting a signal level of a signal by increasing a voltage thereof, or the like method, in order to make the signal be conformable with D/A converting circuit 1016 for processing an applied voltage level of the signal which is applied to a liquid crystal panel.
A standard voltage generating circuit 1019 generates various analog voltages for the gradient display in accordance with a reference voltage VR inputted from a liquid crystal driving power source, and outputs the analog voltages to a D/A converting circuit 1016.
In accordance with the digital display data, which has been subjected to the level conversion by the level shifter circuit 1015, the D/A converting circuit 1016 selects one of the various analog voltages supplied from the standard voltage generating circuit 1019. The analog voltage indicating the gradation display is outputted via an output circuit 1017 from each liquid crystal driving voltage output terminal (hereinafter, just referred to as output terminals) 1018 to each source signal line of the liquid crystal panel.
The output circuit 1017, which is basically a buffer circuit for performing low impedance conversion, is composed of a voltage follower circuit using a differential amplifier circuit, for example.
Next, the standard voltage generating circuit 1019 and D/A converting circuit 1016 are described in more details as to their circuit arrangement.
FIG. 14 illustrates a circuit arrangement example of the standard voltage generating circuit 1019. In case each digital display data for RGB is composed of 6 bits, the standard voltage generating circuit 1019 outputs sixty-four levels of analog voltages corresponding to 26=sixty-four gradation displays. In the following, a specific arrangement thereof will be explained.
The standard voltage generating circuit 1019 is composed of resistive divider circuits, in which resistors R0 to R7 are connected in series, thus having a simplest arrangement. Each of the respective resistors R0 to R7 are composed of eight resistance elements connected in series.
The resistor R0 will be explained as an example. As shown in FIG. 15, R0 is composed of resistance elements R01, R02, . . . R08 connected in series. The other resistors R1 to R7 have the same arrangement. Therefore, the standard voltage generating circuit 1019 is composed of sixty-four resistance elements connected in series, in total.
Moreover, the standard voltage generating circuit 1019 is provided with nine intermediate voltage input terminals for nine levels of reference voltages V′0 V′8 . . . V′56 V′64. Moreover, the intermediate voltage input terminal for the reference voltage V′64 is connected to an end of the resistor R0, meanwhile the intermediate voltage input terminal for the reference voltage V′56 is connected to the other end of the resistor R0, that is, a node between the resistor R0 and R1.
In the same manner, the intermediate voltage input terminals for the reference voltages V′48 V′40 . . . V′08 are connected respectively to nodes between the neighboring pair of the resistors R1 and R2, R3 and R4, . . . R6 and R7. Further, in the resistor R7 the intermediate voltage input terminal for the reference voltage V′0 is connected to one node that is not connected to the resistor R6 (the other one node is connected to the resistor R6).
With this arrangement, it is possible to obtain 64 levels of analog voltages V0 to V63 for gradation display. The 64 levels of analog voltages V0 to V63 include the voltages V1 to V63, which are obtained from the pairs of the neighboring sixty four resistors, and a voltage V0 obtained from the reference voltage V′0. Moreover, in the liquid crystal display apparatus, a polarity of the driving voltage, which is to be supplied to a the pixel electrode in order to reliability thereof, is inverted. That is, where gradation-display-use analog voltages for positive polarity (gradation-display-use positive polarity analog voltages) are +V0 to +V63, gradation-display-use analog voltages for negative polarity (gradation-display-use negative polarity analog voltages) are −V0 to −V63. Furthermore, an output from the standard voltage generating circuit 1019 is outputted in such a manner that each of the gradation-display-use positive polarity analog voltages +V0 to +V63 and each of the gradation-display-use negative polarity analog voltages −V0 to −V63 are outputted from a terminal from which a corresponding counterpart voltage thereof (for example, for the positive polarity analog voltage +V0, is outputted from the terminal from which its counterpart voltage, that is the negative polarity analog voltage −V0, is outputted).
Next, in an example where the standard voltage generating circuit 1019 is composed of a resistive divider circuit, the voltages V0 to V63 are inputted from the standard voltage generating circuit 1019 to the D/A converting circuit 1016.
Next, the D/A converting circuit 1016 will be explained. FIG. 16 shows an example of arrangements of the D/A converting circuit 1016. Note that, the reference numeral 1017 indicates the arrangement of the output circuit (voltage follower circuit) discussed previously.
In the D/A converting circuit 1016, for example, MOS transistors or transmission gates are provided as analog switches so that one of the inputted 64 levels of the voltage V0 to V63 is selected in accordance with the display data composed of the digital signals of 6 bits, and outputted. That is, the switch is turned ON/OFF in accordance with the respective display data (bit 0 to bit 5) composed of the digital signals of 6 bits. In this way, one of the sixty-four levels of voltages is selected and outputted to the output circuit 1017. This is explained below.
Among the digital display data of 6 bits, Bit 0 is an LSB (the Least Significant Bit) and Bit 5 is an MSB (the Most Significant Bit). Each two of the switches forms a switching pair. Thirty two switching pairs (sixty-four switches) are provided to deal with Bit 0, while sixteen switching pairs (thirty-two switches) are provided to deal with Bit 1.
Likewise, a half number of the switching pairs are provided to the next less significant bit. Thus, one switching pair (two switches) is provided to deal with Bit 5. Therefore, there existed 25+24+23+22+21+1=sixty three pairs (one-hundred-and-twenty-six switches) in total.
One end of each switch for Bit 0 is a terminal for receiving one of the voltages V0 to V63. The other end of each switch for Bit 0 is connected that of the mate thereto, and to one end of each switch for Bit 1. Likewise, similar arrangements are repeated until the switches for Bit 5. At last, one line is drawn out of the switches for Bit 5 and connected to the output circuit 1017.
Hereinafter, the switches for Bit 0 to Bit 5 are referred as switch groups SW0 to SW5, respectively. Each switch of the switch groups SW0 to SW5 is controlled in accordance with digital display data (Bit 0 to Bit 5) of 6 bits as follows. In the switch groups SW0 to SW5, one mate of the pairs of the analog switches (in FIG. 16, the mate of a lower position (hereinafter, referred to as lower switches)) are turned ON when their related Bits are 0 (low level). On the contrary, the other mate of the pairs of the analog switches (in FIG. 16, the mate of an upper position (hereinafter, referred to as upper switches)) when their related Bits are 1 (high level).
In FIG. 16, Bit 0 to Bit 5 are (111111). Thus, the upper switches of the all pairs of switches are turned ON, while the lower switches thereof are turned OFF. In this case, the D/A converting circuit 1016 outputs the voltage V63 to the output circuit 1017. Likewise, for example in case where Bit 0 to Bit 5 are (111110), the D/A converting circuit 1016 outputs the voltage V62 to the output circuit 1017. In case where Bit 0 to Bit 5 are (000001), the D/A converting circuit 1016 outputs the voltage V1. Further, in case where Bit 0 to Bit 5 are (000000), the D/A converting circuit 1016 outputs the voltage V0 to the output circuit 1017. In this way, one of the analog voltages V0 to V63 for gradation display is selected so as to realize the gradation display.
Usually, one standard voltage generating circuit 1019 is provided in each source driver IC, and used in a sharing manner. On the other hand, the same number of D/A converting circuits 1016 and output circuits 1017 and the output terminals 1018 are provided (that is, the D/A converting circuits 1016 and output circuits 1017 in the same number as the output terminals 1018), in order that one D/A converting circuit 1016 and one output circuit 1017 are provided for each output terminal 1018.
Moreover, in case of the color display, one output terminal 1018 is provided for each color. In this case, one D/A converting circuit 1016 and one output circuit 1017 are provided for each pixel, or each color.
Specifically, where there provided a 3N number of pixels along a longitudinal direction (horizontal line) of the liquid crystal panel, and the output terminals 1018 respectively for red, green and blue are labeled with the reference characters R, G, and B with reference numerals n (n=1, 2, . . . , N), the output terminals 1018 are shown as R1, G1, B1, R1, G1, B1, . . . , and RN, GN, BN. Suppose, for example, that the liquid crystal panel is driven with eight source drivers IC, each source driver needs a 3N/8 number of D/A converting circuits 1016 and the output circuits 1017.
Incidentally, in reality, the Υ correction is carried out in the gradation display in the liquid crystal display apparatus. The Υ correction adjusts the difference between light transmittance property of liquid crystal materials and visual sense of humans, thereby realizing a natural gradation display. The Υ correction is generally carried out by using the standard voltage generating circuit having an arrangement in which internal resistors are divided unequally (but not equally divided) so as to generate various levels of analog voltages for gradation display.
FIG. 17 illustrates a relationship between gradation display data (digital display data) and a liquid crystal driving output voltage (analog voltage for gradation display). As shown in FIG. 17, with respect to the digital display data, the values of the analog voltage for gradation display shows, on the graph, a line that bents at several points. (Hereinafter, this property of the values is referred to as a bent line property. That is, the values of the analog voltage for gradation display have the bent line property.)
In order to give the bent line property to the values of the analog voltage for gradation display, the standard voltage generating circuit 1019 shown in FIG. 14 is so arranged that the resistive resistance values in the resistors R0, . . . , and R7 are evenly divided into eight, and the resistors R0, . . . , and R7 have such values that the aforementioned Υ correction is realized with the values.
Specifically, the resistance values of the eight resistance elements, for example, the resistance elements R01, R02, . . . , and R08 connected in series forming the resistor R0, have the same resistance values, while the resistors R0, R1, . . . , and R7, which are respectively composed of the eight resistance elements, have resistance values in such a ratio that the aforementioned Υ correction is realized when the resistance values of the resistors R0, R1, . . . , and R7 are in the ratio.
Incidentally, the research and development for the liquid crystal display apparatus have been focused on realization of a larger screen for use in televisions, personal computers and the like. On the other hand, there is a demand for a liquid crystal display apparatus and liquid crystal driving apparatus suitable for use in personal display apparatus for personal terminals such as personal telephones and the like, whose market is rapidly growing.
The liquid crystal display apparatus, in which the liquid crystal driving apparatus is used, and which is suitable for use in the personal terminals, basically have a small screen size. In conformity with the small screen size, the liquid crystal driving apparatus should be small in size and light in weight, and further should have a low power consumption so that a battery can be used for driving.
Here, each switch constituting the D/A converting circuit 1016 is conventionally composed of a CMOS transistor (combination of a PchMOS transistor and an NchMOS transistor), for the reason explained below.
In case of the aforementioned arrangement in which all the inputted gradation standard voltages are inputted into the same D/A converting circuit and the polarity inversion of the gradation standard voltage is carried out, each switch in the D/A converting circuit receive both the reference voltages of high level and reference voltages of low level.
For example, the switch that receives a voltage of +V63 (high level) when the polarity is positive, receives a voltage of −V63 (low level) when the polarity is negative, where the voltages of +V0 to +V31 are of low level (in a low voltage group) while the voltages +V32 to +V63 are of high level (in the high voltage group) when the polarity is positive, while the voltages of −V0 to −V31 are of high level (in a high voltage group) while the voltages −V32 to −V63 are of low level (in the low group) when the polarity is negative.
In this case, if the switches of the D/A converting circuit are constituted solely of a PchMOS transistor, the output of the D/A converting circuit is distorted when the voltage is of low level, while if the switches of the D/A converting circuit are composed solely of an NchMOS transistor, the output of the D/A converting circuit is distorted when the voltage is of high level. Thus, if the switches of the D/A converting circuit are composed solely of either a PchMOS transistor or an NchMOS transistor, normal D/A conversion output may not be attained. Because of this, the two types of transistors are combined to constitute the switches in the prior art. With this arrangement, the PchMOS transistor is mainly operated when the voltage of high level is inputted, while the NchMOS transistor is mainly operated when the voltage of low level is inputted, whereby the switching relating to D/A converting process is normally operated.
However, in the arrangement in which each one switch is composed of the two transistors, a great number of transistors are provided on a chip, resulting in an increase in a substrate area. This gives the driving circuit a large circuit arrangement, that is, causes the liquid crystal display apparatus to be larger (in other words, this hinders miniaturizations of the liquid crystal display apparatus).
Moreover, in case each one switch is composed of the PchMOS transistor and NchMOS transistor in combination, those transistors are formed on the same substrate. In this case, it is a problem that back gate effect due to substrate bias is caused in at least either the PchMOS transistor or NchMOS transistor, thereby causing drop in output voltage.